Process variation is an increasingly important factor in the design of high yielding and high-performance ICs. Because the precise knowledge of variation is becoming an even more integral part of the design process as technology continues to scale, testing techniques are needed to extract, measure, and characterize variation in a given process and link it to circuit performance.
Process variation in IC fabrication is the deviation from intended or designed values for a structure or circuit parameter of concern. Process variation can result in the fluctuation of parameter values and dimensions in both the structural device and interconnect levels, which can influence performance of ICs. Of particular concern are the effects of structural device and interconnect variations caused by increasing lithography complexity and pattern variation on the performances of ICs in the 32 nm and sub-32 nm logic technologies.
Conventionally, IC designers use embedded devices in a test site of a semiconductor chip. The embedded devices can be tested at a time of qualification as a part of the yield/diagnostic strategy to detect the effects of layout-induced variations. In particular, performance of the embedded devices are measured during the design stages to achieve a better understanding of in-die performance variations resulting from across-chip process variations (ACV) such as photo/etch interactions, chemical mechanical planarization (CMP) dishing and erosion, and other process interactions not observed with typical scribe region measurements. Since ring oscillators oscillate at a frequency dependent on the performance of the devices, these circuits are typically used as the embedded devices to detect structural device and interconnect process variation through measurements of their oscillating frequencies.
Conventional design techniques include measuring the embedded device performance based on an initial ACV at the time of qualification of the semiconductor product, and timing the semiconductor product to meet the worst-case conditions and ACV assumptions to account for the process variations. While this technique is adequate in older technologies such as 90 nm, newer technologies such as 32 nm or less are beginning to show increasing effects of cross die variation due to the increasingly smaller geometry effects and the tolerance of building such devices within these advanced technologies. As such, designers utilize increasingly conservative approaches to provide adequate performance guard band to account for the process variations because, even if a portion of a design may be closer to worst-case performance, another portion of the path may have performance margin due to the ACV. In a similar manner, one area of the chip die may exhibit worst-case process effects, while another section, due to ACV, has performance margin. With these design techniques, designs are timed to meet the worst-case conditions and ACV assumptions, resulting in over-designed paths being integrated into the silicon. This increases costs, complicates fabrication processes, and the faster devices added to close timing increase power.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.